BSIM-Bulk MOSFET Model for IC Design - Digital, Analog, RF and High-Voltage

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Chenming Hu (Professor Emeritus, University of California, Berkeley, CA, USA) Harshit Agarwal (Center Manager and Postdoctoral Researcher, Berkeley Device Modeling Center, Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, USA)

BSIM-Bulk MOSFET Model for IC Design - Digital, Analog, RF and High-Voltage

Chenming Hu (Professor Emeritus, University of California, Berkeley, CA, USA), Harshit Agarwal (Center Manager and Postdoctoral Researcher, Berkeley Device Modeling Center, Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, USA), Chetan Gupta (Principal Engineer, Micron Technologies, India) , Yogesh Singh Chauhan (Professor, Department of Electrical Engineering, Indian Institute of Technology Kanpur, India)

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English

Woodhead Publishing
03 May 2023

Manufacturing industries; Materials science; Engineering skills & trades; Electronics & communications engineering; Electronic devices & materials

Series: Woodhead Publishing Series in Electronic and Optical Materials

BSIM-Bulk MOSFET Model for IC Design - Digital, Analog, RF and High-Voltage provides in-depth knowledge of the internal operation of the model. The authors not only discuss the fundamental core of the model, but also provide details of the recent developments and new real-device effect models. In addition, the book covers the parameter extraction procedures, addressing geometrical scaling, temperatures, and more. There is also a dedicated chapter on extensive quality testing procedures and experimental results. This book discusses every aspect of the model in detail, and hence will be of significant use for the industry and academia.

Those working in the semiconductor industry often run into a variety of problems like model non-convergence or non-physical simulation results. This is largely due to a limited understanding of the internal operations of the model as literature and technical manuals are insufficient. This also creates huge difficulty in developing their own IP models. Similarly, circuit designers and researcher across the globe need to know new features available to them so that the circuits can be more efficiently designed.

By: Chenming Hu (Professor Emeritus University of California Berkeley CA USA), Harshit Agarwal (Center Manager and Postdoctoral Researcher, Berkeley Device Modeling Center, Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, USA), Chetan Gupta (Principal Engineer, Micron Technologies, India), Yogesh Singh Chauhan (Professor, Department of Electrical Engineering, Indian Institute of Technology Kanpur, India)
Imprint: Woodhead Publishing
Country of Publication: United States
Dimensions: Height: 229mm, Width: 152mm,
Weight: 1.000kg
ISBN: 9780323856775
ISBN 10: 0323856772
Series: Woodhead Publishing Series in Electronic and Optical Materials
Pages: 270
Publication Date: 03 May 2023
Audience: Professional and scholarly , Undergraduate
Format: Paperback
Publisher's Status: Active

1. Background 2. BSIM-BULK Core Model 3. Real Device Effects 4. Leakage current and thermal effects 5. BSIM-BULK Charge and Capacitance Model 6. Noise and RF Modeling 7. Junction Diode and Layout Dependent Parasitic Model 8. Compact Modeling of High Voltage Devices 9. Parameter Extraction 10. BSIM-BULK Model Quality Testing

Chenming Hu is Distinguished Chair Professor Emeritus at UC Berkeley. He was the Chief Technology Officer of TSMC and founder of Celestry Design Technologies. He is best known for developing the revolutionary 3D transistor FinFET that powers semiconductor chips beyond 20nm. He also led the development of BSIM-- the industry standard transistor model that is used in designing most of the integrated circuits in the world. He is a member of the US Academy of Engineering, the Chinese Academy of Science, and Academia Sinica. His honors include the Asian American Engineer of the Year Award, IEEE Andrew Grove Award and Solid Circuits Award as well as Nishizawa Medal, and UC Berkeley's highest honor for teaching-- the Berkeley Distinguished Teaching Award. Harshit Agarwal received the PhD degree from Indian Institute of Technology Kanpur, India in 2017. He is currently working as center manager and post-doc fellow at Berkeley Device Modeling Centre, BSIM group, University of California Berkeley, Berkeley, USA. He has been involved in the development of multi-gate and bulk MOSFET models. He is also involved in the modeling and characterization of advanced steep sub-threshold slope devices like negative capacitance FETs, tunnel FET etc. He has authored several papers in the field of semiconductor device modeling, simulation and characterization. He is a Co-Developer of BSIM-BULK (formerly BSIM6) industry standard models for BULK-MOSFET. He has published 8 journal papers and 10 conference papers all on the development of the BSIM-BULK model. His current research interests include semiconductor device physics, modeling, and characterization. Yogesh Singh Chauhan is a Professor at the Indian Institute of Technology Kanpur. His research interests include the physics, characterization, and modeling of nanoscale semiconductor devices, and RF circuit design. He is the developer of several industry standard models, including the BSIM-BULK (BSIM6), BSIM-IMG, BSIM-CMG and ASM-HEMT models.