Power-Aware Computer Systems: First International Workshop, PACS 2000 Cambridge, MA, USA, November 12,...

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B. Falsafi T.N. Vijaykumar

Power-Aware Computer Systems

First International Workshop, PACS 2000 Cambridge, MA, USA, November 12, 2000 Revised Papers...

B. Falsafi, T.N. Vijaykumar

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English

Springer-Verlag Berlin and Heidelberg GmbH & Co. K
11 July 2001

Microprocessors; Computer architecture & logic design

Series: Lecture Notes in Computer Science

This book constitutes the thoroughly refereed post-proceedings of the First International Workshop on Power-Aware Computer Systems, PACS 2000, held in Cambridge, MA, USA, in November 2000. The 11 revised full papers presented were carefully reviewed, selected, and revised for inclusion in the book. This book addresses power/energy-awareness at all levels of computer systems. The papers are organized in sections on power-aware microarchitectural/circuit techniques, application/compiler optimization, exploiting IPC/memory slack, and power/performance models and tools.

Edited by: B. Falsafi, T.N. Vijaykumar
Imprint: Springer-Verlag Berlin and Heidelberg GmbH & Co. K
Country of Publication: Germany
Edition: 2001 ed.
Volume: 2008
Dimensions: Height: 235mm, Width: 155mm, Spine: 9mm
Weight: 540g
ISBN: 9783540423294
ISBN 10: 354042329X
Series: Lecture Notes in Computer Science
Pages: 158
Publication Date: 11 July 2001
Audience: Professional and scholarly , Undergraduate
Format: Paperback
Publisher's Status: Active

Power-Aware Microarchitectural/Circuit Techniques.- System-Level Design Methods for Low-Energy Architectures Containing Variable Voltage Processors.- Ramp Up/Down Functional Unit to Reduce Step Power.- An Adaptive Issue Queue for Reduced Power at High Performance.- Application/Compiler Optimizations.- Dynamic Memory Oriented Transformations in the MPEG4 IM1-Player on a Low Power Platform.- Exploiting Content Variation and Perception in Power-Aware 3D Graphics Rendering.- Compiler-Directed Dynamic Frequency and Voltage Scheduling.- Exploiting IPC/Memory Slack.- Cache-Line Decay: A Mechanism to Reduce Cache Leakage Power.- Dynamically Reconfiguring Processor Resources to Reduce Power Consumption in High-Performance Processors.- Power/Performance Models and Tools.- TEM2P2EST: A Thermal Enabled Multi-model Power/Performance ESTimator.- Power-Performance Modeling and Tradeoff Analysis for a High End Microprocessor.- A Comparison of Two Architectural Power Models.