Novel Architecture of Analog to Digital Converter

Narula Swina

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English

Self Publisher
28 February 2023

Examinations & assessment; Scientific standards; Mensuration & systems of measurement; Instruments & instrumentation engineering

Summary
Details

A number of digital applications e.g. professional cameras, voice communication, video digitizers, data imaging and many more require low power, high speed, and high resolution analog to digital converters. But for high speed data communication systems with increased resolution and high sampling rates, different linear and nonlinear errors of ADCs come in picture which is a big

challenge for design engineers to remove.

A unique digital background calibration technique, a combination of signal dependent dithering with butterfly shuffler is proposed here for multi-bit, SHA-less 16-bit, 125 MS/s Pipelined ADC. The purpose of the research work was to integrate different stages of different sizes to achieve 16-bit error-free output at high sampling rate by using unique background calibration technique for SHA-less circuit. Because the achieved values of SNDR and SFDR are high with low power consumption, so this proposed ADC is suitable for high resolution applications like video communication. Without using sample and hold amplifier we saved power and reduced noise interference. Additional advantage of SHA removal is to use a smaller input sampling capacitor which increases ADC's drivability. A new timing diagram is also proposed here to resolve the

sampling clock skew. The ultimate multi-bit front-end proposed here helped to save further power.

The proposed comparator is able to avoid the kickback as compared to traditional comparators. For the initial multi-bit stage, a two-stage gain boosted amplifier is used to achieve high gain and to reduce the nonlinear gain errors. Because the non-idealities of Op-amp and capacitor

mismatching errors, the ADC transfer function may achieve erroneous values by DNL errors, so the proposed technique is made capable to remove linear gain and offset errors and capacitor mismatching errors. Also the small signal linearity errors removed with the proposed architecture of 16-bit Pipelined ADC. Along with these advantages, high values of SNDR and SFDR has

achieved, which is a top most indicator to distinguish the signal out from other noise and spurious frequencies.

By: Narula Swina
Imprint: Self Publisher
Dimensions: Height: 229mm, Width: 152mm, Spine: 7mm
Weight: 191g
ISBN: 9798889950554
Pages: 136
Publication Date: 28 February 2023
Audience: General/trade , ELT Advanced
Format: Paperback
Publisher's Status: Active