Microprocessor Architecture

From Simple Pipelines to Chip Multiprocessors

Jean-Loup Baer (University of Washington)

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English

Cambridge University Press
07 December 2009

Microprocessors; Computer architecture & logic design

This book gives a comprehensive description of the architecture of microprocessors from simple in-order short pipeline designs to out-of-order superscalars. It discusses topics such as: • The policies and mechanisms needed for out-of-order processing such as register renaming, reservation stations, and reorder buffers

• Optimizations for high performance such as branch predictors, instruction scheduling, and load-store speculations • Design choices and enhancements to tolerate latency in the cache hierarchy of single and multiple processors • State-of-the-art multithreading and multiprocessing emphasizing single chip implementations Topics are presented as conceptual ideas, with metrics to assess the performance impact, if appropriate, and examples of realization. The emphasis is on how things work at a black box and algorithmic level. The author also provides sufficient detail at the register transfer level so that readers can appreciate how design features enhance performance as well as complexity.

By: Jean-Loup Baer (University of Washington)
Imprint: Cambridge University Press
Country of Publication: United Kingdom
Dimensions: Height: 257mm, Width: 180mm, Spine: 25mm
Weight: 840g
ISBN: 9780521769921
ISBN 10: 0521769922
Pages: 382
Publication Date: 07 December 2009
Audience: College/higher education , Professional and scholarly , Primary , Undergraduate
Format: Hardback
Publisher's Status: Active

1. Introduction; 2. The basics; 3. Superscalar processors; 4. Front-end: branch prediction, instruction fetching, and register renaming; 5. Back-end: instruction scheduling, memory access instructions, and clusters; 6. The cache hierarchy; 7. Multiprocessors; 8. Multithreading and (chip) multiprocessors; 9. Current limitations and future challenges.

Jean-Loup Baer is Professor Emeritus of Computer Science and Engineering at the University of Washington, where he has been since 1969. Professor Baer is the author of Computer Systems Architecture and more than 100 refereed papers. He is a Guggenheim Fellow, an ACM Fellow, and an IEEE Fellow. Baer has held several editorial positions, including editor-in-chief of the Journal of VLSI and Computer Systems and editor of the IEEE Transactions on Computers, the IEEE Transactions on Parallel and Distributed Systems, and the Journal of Parallel and Distributed Computing. He has served as General Chair and Program Chair of several conferences, including ISCA and HPCA.

Reviews for Microprocessor Architecture: From Simple Pipelines to Chip Multiprocessors

'The book gives a comprehensive and profound description of the architecture of microprocessors from simple in-order short pipeline designs to out-of-order superscalers ... The book is very well structured with good presentation of the material. Each chapter finishes with many exercises, examples and additional literature. All the references are very up-to-date. As a conclusion I warmly recommend this book as a textbook for a course or just as a reference book.' Zentralblatt MATH Professor Baer has developed an extremely appropriate and timely textbook for computer architecture, with a focus on how processors work, and how select micro-architectural features work. He is an excellent teacher, and has effectively presented and explained the concepts. The text covers all the major subjects necessary for a semester-long course in computer architecture. Patrick Crowley, Washington University in St. Louis Overall, I believe that the book will serve as a useful textbook for explaining concepts related to the architecture of microprocessors to undergraduate and graduate students. S. V. Nagaraj, Computing Reviews