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Digital Logic Design Using Verilog: Coding and RTL Synthesis by Vaibbhav Taraate at Abbey's Bookshop,
Digital Logic Design Using Verilog: Coding and RTL Synthesis
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Vaibbhav Taraate

Digital Logic Design Using Verilog

Coding and RTL Synthesis

Vaibbhav Taraate

$214.95   $171.85

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English
Springer Verlag, Singapore
02 November 2022
Circuits & components; Computer architecture & logic design
This second edition focuses on the thought process of digital design and implementation in the context of VLSI and system design. It covers the Verilog 2001 and Verilog 2005 RTL design styles, constructs and the optimization at the RTL and synthesis level. The book also covers the logic synthesis, low power, multiple clock domain design concepts and design performance improvement techniques. The book includes 250 design examples/illustrations and 100 exercise questions. This volume can be used as a core or supplementary text in undergraduate courses on logic design and as a text for professional and vocational coursework. In addition, it will be a hands-on professional reference and a self-study aid for hobbyists. 
By:  
Imprint:   Springer Verlag, Singapore
Country of Publication:   Singapore
Edition:   2nd ed. 2022
Dimensions:   Height: 235mm,  Width: 155mm, 
Weight:   955g
ISBN:   9789811632013
ISBN 10:   9811632014
Pages:   604
Publication Date:  
Audience:   Professional and scholarly ,  Undergraduate
Format:   Paperback
Publisher's Status:   Active
Introduction.- Combinational Logic Design (Part I).- Combinational Logic Design (Part II).- Combinational Design Guidelines.- Sequential Logic Design.- Sequential Design Guidelines.- Complex Designs using Verilog RTL.- Finite State Machines.- Simulation Concepts and PLD Based Designs.- RTL Synthesis.- Static Timing Analysis (STA).- Constraining Design.- Multiple Clock Domain Designs.- Low Power Design.- RTL Design for SOCs.

Vaibbhav Taraate is an entrepreneur and mentor at “1 Rupee S T”. He holds B.E. (Electronics) degree from Shivaji University, Kolhapur (1995) and received a Gold Medal for standing first in all engineering branches. He completed his M.Tech. (Aerospace Control and Guidance) at the Indian Institute of Technology (IIT) Bombay, India, in 1999. He has over 18 years of experience in semi-custom ASIC and FPGA design, primarily using HDL languages such as Verilog, VHDL and SystemVerilog. He has worked with multinational corporations as a consultant, senior design engineer, and technical manager. His areas of expertise include RTL design using VHDL, RTL design using Verilog, complex FPGA-based design, low power design, synthesis and optimization, static timing analysis, system design using microprocessors, high-speed VLSI designs, and architecture design of complex SOCs.

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