Design Rules in a Semiconductor Foundry

Eitan N. Shauly (Tower Semiconductor Ltd, Israel)

$809

Hardback

Not in-store but you can order this
How long will it take?

Availability Information

We source books from suppliers in Australia and overseas. For books we don't currently have in stock, the time it takes to get them from our suppliers can vary widely - from a few days to a few months - so we check each book with each supplier to determine the expected time it will take to be supplied to us.

We then advise you accordingly. If the time taken to get any book is too long for you, you can let us know and we will cancel or adjust your order, and refund as required.

To find out the anticipated arrival time for specific items prior to ordering, please contact us by phone or email:

Phone +61 2 9264 3111, or 1800 4 BOOKS (1800 4 26657) if outside Sydney:
option 1 Abbey's Bookshop (Crime, History, Science, Kids & more) • info@abbeys.com.au
option 2 Language Book Centre (ESL & Foreign Languages) • language@abbeys.com.au
option 3 Galaxy Bookshop (Sci-fi, Fantasy, Romance, Graphic Novels) • sf@galaxybooks.com.au

QTY:

English

Jenny Stanford Publishing
30 November 2022

Is designed to serve as a comprehensive and up-to-date manual for process, device, layout, and design engineers Covers topics that designers as well as layout and process engineers deal with every day, such as front-end-of-line (FEOL) and back-end-of-line BEOL DRs, coverage DRs, stressors DRs, and modeling, foundry reliability, and advance (20 nm) step-by-step process flow Can be used by those studying semiconductors and microelectronics as well as students and researchers in the fields of electrical engineering, physics, materials engineering, and chemical engineering

Edited by: Eitan N. Shauly (Tower Semiconductor Ltd Israel)
Imprint: Jenny Stanford Publishing
Country of Publication: Singapore
Dimensions: Height: 229mm, Width: 152mm,
ISBN: 9789814968003
ISBN 10: 9814968005
Pages: 808
Publication Date: 30 November 2022
Audience: General/trade , ELT Advanced
Format: Hardback
Publisher's Status: Active

1. Layout Design Rules: Definition, Setting and Scaling 2. Front-End-Of-Line Topological Design Rules 3. Back-End-Of-Line Topological Design Rules 4. Coverage Rules and Insertion Utilities 5. Design Rules, Guidelines and Modelling for Analog Modules 6. Stress Related Layout Design Rules and Modelling 7. Dedicated Design Rules for Memory Modules 8. Planar CMOS Process Flow for Digital, Mixed-Signal and RFCMOS Applications 9. Reliability Driven Design Rules

Eitan N. Shauly is the director of integration at Tower Semiconductor Ltd., Israel, since 1998. He has been with the organization since 1989, initially as a diffusion and ion implantation engineer and a device/integration engineer and later focusing on process integration, modeling, and design rules as well as incorporating new technology in the company's foundries. Dr Shauly also teaches courses related to VLSI technology in the Faculty of Materials Science and Engineering, Technion - Israel Institute of Technology, Haifa, Israel. He received his BSc (1989) in materials engineering from Ben-Gurion University, Beer-Sheva, Israel, and MSc (1995) and PhD (2001) in materials engineering from the Technion - Israel Institute of Technology.