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Spacer Engineered FinFET Architectures: High-Performance Digital Circuit Applications by Sudeb Dasgupta at Abbey's Bookshop,
Spacer Engineered FinFET Architectures: High-Performance Digital Circuit Applications
— —
Sudeb Dasgupta Brajesh Kumar Kaushik (Indian Institute of Technology Roorkee, Uttareakhand, India)

Spacer Engineered FinFET Architectures

High-Performance Digital Circuit Applications

Sudeb Dasgupta,  Brajesh Kumar Kaushik (Indian Institute of Technology Roorkee, Uttareakhand, India),  Pankaj Kumar Pal (Indian Institute of Technology-Roorkee, India)

$94.99

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English
CRC Press
30 June 2020
Nanotechnology; Circuits & components
This book focusses on the spacer engineering aspects of novel MOS-based device–circuit co-design in sub-20nm technology node, its process complexity, variability, and reliability issues. It comprehensively explores the FinFET/tri-gate architectures with their circuit/SRAM suitability and tolerance to random statistical variations.
By:   , , , , ,
Imprint:   CRC Press
Country of Publication:   United Kingdom
Dimensions:   Height: 234mm,  Width: 156mm, 
Weight:   260g
ISBN:   9780367573553
ISBN 10:   0367573555
Pages:   138
Publication Date:  
Audience:   College/higher education ,  General/trade ,  Primary ,  ELT Advanced
Format:   Paperback
Publisher's Status:   Active
Preface About the Authors Chapter 1 ◾ Introduction to Nanoelectronics Chapter 2 ◾ Tri-Gate FinFET Technology and Its Advancement Chapter 3 ◾ Dual-k Spacer Device Architecture and Its Electrostatics Chapter 4 ◾ Capacitive Analysis and Dual-k FinFET-Based Digital Circuit Design Chapter 5 ◾ Design Metric Improvement of a Dual-k–Based SRAM Cell Chapter 6 ◾ Statistical Variability and Sensitivity Analysis INDEX

Sudeb Dasgupta, Brajesh Kumar Kaushik, Pankaj Kumar Pal

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